Structures for a ferroelectric field-effect transistor and related methods

ABSTRACT

Structures for a ferroelectric field-effect transistor and methods of forming a structure for a ferroelectric field-effect transistor. The structure comprises a gate stack having a ferroelectric layer, a first conductor layer, and a second conductor layer positioned in a vertical direction between the first conductor layer and the ferroelectric layer. The first conductor layer comprises a first material, the second conductor layer comprises a second material different from the first material, and the second conductor layer is in direct contact with the ferroelectric layer.

BACKGROUND

The disclosure relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a ferroelectric field-effect transistor and methods of forming a structure for a ferroelectric field-effect transistor.

A field-effect transistor generally includes a source, a drain, a semiconductor body supplying a channel region between the source and drain, and a gate electrode overlapped with the channel region. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and drain to produce a device output current. A ferroelectric field-effect transistor is a metal-insulator-semiconductor field-effect transistor in which the gate dielectric is replaced by a layer containing a ferroelectric material. The threshold voltage of the ferroelectric field-effect transistor depends on the polarization state of the ferroelectric layer.

Improved structures for a ferroelectric field-effect transistor and methods of forming a structure for a ferroelectric field-effect transistor are needed.

SUMMARY

In an embodiment of the invention, a structure for a ferroelectric field-effect transistor is provided. The structure comprises a gate stack including a ferroelectric layer, a first conductor layer, and a second conductor layer positioned in a vertical direction between the first conductor layer and the ferroelectric layer. The first conductor layer comprises a first material, the second conductor layer comprises a second material different from the first material, and the second conductor layer is in direct contact with the ferroelectric layer.

In an embodiment of the invention, a method of forming a structure for a ferroelectric field-effect transistor is provided. The method comprises forming a gate stack including a ferroelectric layer, a first conductor layer, and a second conductor layer positioned in a vertical direction between the first conductor layer and the ferroelectric layer. The first conductor layer comprises a first material, the second conductor layer comprises a second material different from the first material, and the second conductor layer is in direct contact with the ferroelectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.

FIG. 1 is a cross-sectional view of a structure in accordance with embodiments of the invention.

FIG. 2 is a cross-sectional view of a structure in accordance with alternative embodiments of the invention.

DETAILED DESCRIPTION

With reference to FIG. 1 and in accordance with embodiments of the invention, a ferroelectric field-effect transistor 10 is formed using a semiconductor substrate 12 that is comprised of a semiconductor material, such as single-crystal silicon. The ferroelectric field-effect transistor 10 may be fabricated by front-end-of-line processing as a device structure in an active device region of the semiconductor substrate 12. The ferroelectric field-effect transistor 10 may include a multi-layer gate stack 14 that is positioned on the semiconductor substrate 12. The gate stack 14 may be formed by depositing a layer stack including thin films of the different materials and patterning the layer stack with photolithography and etching processes.

The gate stack 14 includes an interfacial layer 16 that is arranged on the semiconductor substrate 12 and a ferroelectric layer 18 that is arranged on the interfacial layer 16. The interfacial layer 16 is positioned in a vertical direction between the ferroelectric layer 18 and the semiconductor substrate 12. The interfacial layer 16 may be comprised of a dielectric material, such as silicon dioxide either grown or deposited, that is an electrical insulator. The ferroelectric layer 18 may be comprised of a ferroelectric material, such as a high-k dielectric material like hafnium oxide or zirconium oxide, that is deposited, for example, by atomic layer deposition. In an embodiment, the ferroelectric material of the ferroelectric layer 18, which is an electrical insulator, may have a permittivity that is greater than the permittivity of the dielectric material of the interfacial layer 16. The ferroelectric material constituting the ferroelectric layer 18 may be crystallized by an anneal following deposition. In an embodiment, the ferroelectric layer 18 may have a thickness TO that is greater than or equal to 5 nanometers. In an embodiment, the ferroelectric layer 18 may be crystalline with an orthorhombic phase that is ferroelectric. In an embodiment, the thickness T0 of the ferroelectric layer 18 may be greater than or equal to 5 nanometers, and the ferroelectric layer 18 may be crystalline with an orthorhombic phase that is ferroelectric.

The gate stack 14 of the ferroelectric field-effect transistor 10 includes a gate electrode that is arranged on the ferroelectric layer 18. The gate electrode may include multiple conductor layers 22, 24, 26 in which the conductor layer 24 is disposed in a vertical direction between the conductor layer 22 and the conductor layer 26. The conductor layer 22 has an interface with the ferroelectric layer 18 and, in an embodiment, the conductor layer 22 may have a surface that is in direct contact with an adjacent surface of the ferroelectric layer 18. The conductor layer 24 has an interface with the conductor layer 22 and, in an embodiment, the conductor layer 24 may have a surface that is in direct contact with an adjacent surface of the conductor layer 22. The conductor layer 26 has an interface with the conductor layer 24 and, in an embodiment, the conductor layer 26 may have a surface that is in direct contact with an adjacent surface of the conductor layer 24. A conductor layer 28 comprised of, for example, doped polysilicon may be disposed on the conductor layer 26.

The conductor layer 24 is comprised of a different material than the conductor layer 22, and the conductor layer 24 is also comprised of a different material than the conductor layer 26. The conductor layer 22 and the conductor layer 26 may be comprised of the same material. In an embodiment, the conductor layer 22 and the conductor layer 26 may be comprised of a work function metal. In an embodiment, the conductor layer 22 and the conductor layer 26 may be comprised of titanium nitride. In an embodiment, the conductor layer 24 may be comprised of a metal that getters a reactive species, such as oxygen, that may be present in, or introduced into, the gate stack 14. In an embodiment, the conductor layer 24 may be comprised of aluminum. In an embodiment, the conductor layer 24 may exclusively contain aluminum.

In an embodiment, the conductor layer 22 may have a thickness T1 that is less than or equal to 0.5 nanometers and greater than or equal to 0.1 nanometers. The thickness T1 of the conductor layer 22 may be measured from the interface with the ferroelectric layer 18 to the interface with the conductor layer 24. The thickness T2 of the conductor layer 26 may be measured from the interface with the conductor layer 24 to the interface with the conductor layer 28. In an embodiment, the thickness T2 of the conductor layer 26 may be greater than the thickness T1 of the conductor layer 22. The thickness T0 of the ferroelectric layer 18 may be measured from the interface with the interfacial layer 16 to the interface with the conductor layer 22.

The conductor layer 24 may be located in close proximity to the ferroelectric layer 18 in order to prevent reactions between a reactive species, such as oxygen, and the material of the conductor layer 22. For example, the reactive species that is gettered by the conductor layer 24 may originate from the ferroelectric layer 18. In an embodiment, the conductor layer 24 may be positioned within a distance D1 of less than or equal 0.5 nanometers and greater than or equal to 0.1 nanometers from the ferroelectric layer 18 in order to provide the required gettering function. The distance D1 may be measured from the interface between the conductor layer 24 and the conductor layer 22 to the interface between the conductor layer 22 and the ferroelectric layer 18. The thickness T1 of the conductor layer 22 may be equal to the distance D1 between the conductor layer 24 and the ferroelectric layer 18. The gettering of the reactive species may prohibit the formation of a reacted layer at the interface between the conductor layer 22 and the ferroelectric layer 18, which promotes direct contact between the conductor layer 22 and the ferroelectric layer 18.

The ferroelectric material constituting the ferroelectric layer 18 is characterized by a pair of stable remanent polarization states that are persistent and that can be reversibly varied in response to an electric field applied from the gate electrode. The pair of stable remanent polarization states are appropriate for use as the logic states of a nonvolatile memory bitcell. The remnant polarization states of the ferroelectric material in the ferroelectric layer 18 determine threshold voltage shifts reflecting memory states stored by the ferroelectric field-effect transistor

The ferroelectric field-effect transistor 10 includes sidewall spacers 32 comprised of a dielectric material, such as silicon nitride, that is conformally deposited and anisotropically etched. The ferroelectric field-effect transistor 10 includes source/drain regions 34, 36 may be formed by, for example, ion implantation in the semiconductor substrate 12. The gate stack 14 may operate to self-align the implantation, and the gate stack 14 may be arranged in a lateral direction between the source/drain region 34 and the source/drain region 36. The source/drain regions 34, 36 may be doped (e.g., heavily doped) with a concentration of a dopant, such as an n-type dopant (e.g., arsenic or phosphorus) that provides n-type conductivity. Alternatively, source/drain regions 34, 36 may be doped (e.g., heavily doped) with a concentration of a p-type dopant (e.g., boron) that provides p-type conductivity. As used herein, the term “source/drain region” means a doped region of semiconductor material that can function as either a source or a drain of a ferroelectric field-effect transistor.

Generally, the ferroelectric field-effect transistor 10 may exhibit a fast operation speed, low power requirements, and a non-destructive read capability as a memory device. The material of the conductor layer 24 may be chosen to be a getter for oxygen. The close proximity of the conductor layer 24 to the ferroelectric layer 18 may prevent the formation of an interfacial layer, such as a layer containing titanium, nitrogen, and oxygen, between the conductor layer 22 and the oxygen-containing ferroelectric layer 18. As a result, the ferroelectric field-effect transistor 10 may be characterized by a threshold voltage for each remnant polarization state that exhibits less shift with an increasing number of endurance cycles.

With reference to FIG. 2 and in accordance with alternative embodiments, a conductor layer 40 and a conductor layer 42 may be added to the gate electrode of the gate stack 14. The conductor layer 40 is disposed in a vertical direction between the conductor layer 26 and the conductor layer 42. The conductor layer 40 has an interface with the conductor layer 26 and, in an embodiment, the conductor layer 40 may have a surface that is in direct contact with an adjacent surface of the conductor layer 26. Similarly, the conductor layer 42 has an interface with the conductor layer 40 and, in an embodiment, the conductor layer 42 may have a surface that is in direct contact with a surface of the conductor layer 40.

The conductor layer 40 is comprised of a different material than the conductor layer 42. In an embodiment, the conductor layer 40 may be comprised of the same material (e.g., aluminum) as the conductor layer 24. In an embodiment, the conductor layer 42 may be comprised of the same material (e.g., titanium nitride) as the conductor layer 22 and the conductor layer 26.

The conductor layer 24 is positioned in closer proximity to the ferroelectric layer 18 than the conductor layer 40. In an embodiment, the conductor layer 40 may be positioned within a distance D2 of greater than or equal 1.5 nanometers from the ferroelectric layer 18. The distance D2 may be measured from the interface between the conductor layer 40 and the conductor layer 26 to the interface between the conductor layer 22 and the ferroelectric layer 18. The distance D2 is greater than the distance D1 between the conductor layer 24 and the ferroelectric layer 18. The conductor layer 40 may function as a getter to prevent reactions between the material of the conductor layer 42 and a reactive species, such as oxygen.

The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.

References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/−10% of the stated value(s).

References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction within the horizontal plane.

A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. Different features “overlap” if a feature extends over, and covers a part of, another feature.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. 

1. A structure for a ferroelectric field-effect transistor, the structure comprising: a gate stack including a ferroelectric layer, a first conductor layer, and a second conductor layer positioned in a vertical direction between the first conductor layer and the ferroelectric layer, the first conductor layer comprising a first material, the second conductor layer comprising a second material different from the first material, and the second conductor layer in direct contact with the ferroelectric layer.
 2. The structure of claim 1 wherein the first material of the first conductor layer is configured to getter a reactive species.
 3. The structure of claim 2 wherein the reactive species is oxygen, and the ferroelectric layer comprises hafnium oxide.
 4. The structure of claim 1 wherein the ferroelectric layer comprises hafnium oxide, the first material is aluminum, and the second material is titanium nitride.
 5. The structure of claim 1 wherein the first conductor layer is positioned within a distance of less than or equal to 0.5 nanometers and greater than or equal to 0.1 nanometers from the ferroelectric layer.
 6. The structure of claim 5 wherein the second conductor layer has thickness that is equal to the distance.
 7. The structure of claim 1 wherein the gate stack further includes a third conductor layer, the first conductor layer is positioned in the vertical direction between the third conductor layer and the second conductor layer, and the third conductor layer is thicker than the second conductor layer.
 8. The structure of claim 7 wherein the third conductor layer comprises the second material.
 9. The structure of claim 1 wherein the gate stack further includes a third conductor layer and a fourth conductor layer positioned in the vertical direction between the third conductor layer and the first conductor layer, the third conductor layer comprises the first material, and the fourth conductor layer comprises the second material.
 10. The structure of claim 9 wherein the first conductor layer is positioned within a first distance of less than or equal to 0.5 nanometers and greater than or equal to 0.1 nanometers from the ferroelectric layer, and the third conductor layer is positioned within a second distance of greater than or equal to 1.5 nanometers from the ferroelectric layer.
 11. The structure of claim 9 wherein the first material is aluminum.
 12. The structure of claim 11 wherein the second material is titanium nitride.
 13. The structure of claim 9 wherein the first material is exclusively aluminum.
 14. The structure of claim 1 further comprising: a semiconductor substrate; a first source/drain region in the semiconductor substrate; and a second source/drain region in the semiconductor substrate, wherein the gate stack is positioned on the semiconductor substrate, and the gate stack is arranged in a lateral direction between the first source/drain region and the second source/drain region.
 15. The structure of claim 1 wherein the ferroelectric layer has a thickness that is greater than or equal to 5 nanometers, and the ferroelectric layer is crystalline with an orthorhombic phase that is ferroelectric.
 16. A method of forming a structure for a ferroelectric field-effect transistor, the method comprising: forming a gate stack including a ferroelectric layer, a first conductor layer, and a second conductor layer positioned in a vertical direction between the first conductor layer and the ferroelectric layer, wherein the first conductor layer comprises a first material, the second conductor layer comprises a second material different from the first material, and the second conductor layer is in direct contact with the ferroelectric layer.
 17. The method of claim 16 wherein the ferroelectric layer comprises hafnium oxide, the first material is aluminum, and the second material is titanium nitride.
 18. The method of claim 17 wherein the first conductor layer is positioned within a distance of less than or equal to 0.5 nanometers and greater than or equal to 0.1 nanometers from the ferroelectric layer.
 19. The method of claim 16 wherein the gate stack further includes a third conductor layer and a fourth conductor layer positioned in the vertical direction between the third conductor layer and the first conductor layer, the third conductor layer comprises the first material, and the fourth conductor layer comprises the second material.
 20. The method of claim 19 wherein the first conductor layer is positioned within a first distance of less than or equal to 0.5 nanometers and greater than or equal to 0.1 nanometers from the ferroelectric layer, and the third conductor layer is positioned within a second distance of greater than or equal to 1.5 nanometers from the ferroelectric layer. 